1. Field of the Invention
The present invention relates generally to semiconductor memory modules and more specifically to a memory module in which timing differences among memory units are eliminated by balancing their parasitic capacitive loads.
2. Description of the Related Art
As shown in FIG. 1, the current semiconductor memory module is comprised of a plurality of integrated-circuit memory units (packages) divided into two groups according to clock pulse sequences supplied from clock terminals CLK0 and CLK1. For one thing, memory modules do not necessarily have an even-number of memory units, the clock groups have different numbers of memory units. In FIG. 1, nine memory units U0 to U8 are shown divided into a first group of chips U0 to U4 and a second group of chips U5 to U8, the first group being driven by clock pulses from terminal CLK0 and the second group by clock pulses from terminal CLK1. Further, design considerations may dictate that memory units are divided into a plurality of clock groups so that each group may have a different number of memory units from other groups.
Because of the high clock frequency, the lines connecting the clock terminals CLK0 and CLK1 to the clock inputs of the respective memory units can be considered as transmission lines involving parasitic capacitance. To minimize the differences in parasitic capacitance among the memory units, the clock lines are patterned so that they have equal length. However, the clock source of the terminal CLK0 is required to drive one memory unit greater than is required for the clock source of terminal CLK1. This difference in load between the clock sources causes a time delay At between the point at which the rising edge of the CLK1 pulse passes the threshold and the point at which the rising edge of the CLK0 clock pulse passes the threshold as shown in FIG. 2. Setup time and hold time are defined. The setup time (tS) starts when a signal changes state and lasts until the rising edge of a clock pulse crosses the threshold and the hold time (tH) starts when the clock pulse crosses the threshold and lasts until the signal changes state. The time window "tWindow" (which is equal to the sum of the setup and hold times) of clock source CLK0 is delayed by At with respect to the time window of clock source CLK1 and hence the total time window tWindow is lengthened by .DELTA.t. This is undesirable from the performance viewpoint since it reduces the operating margin of the module. Furthermore, the clock skew .DELTA.t causes the access time (tAC) and data hold time (tOH) for output data of each clock group to differ from those of the other clock group.
In order to overcome the clock-skew problem, Intel's PC100 memory module includes a dummy capacitor 10, which is connected to the clock terminal CLK1, as shown in FIG. 3. Since the value of this capacitor is equal to the capacitance which the clock input of each memory unit has, the load capacitance of each clock source is balanced with the load capacitance of the other clock source. However, since the load capacitance of the clock input of each memory unit depends largely on design, production process and operating voltage, it is difficult to precisely determine the value of the dummy capacitor.
Similar problem occurs with memory modules in which data mask signals (DQMB) are used to drive its memory units. As shown in FIG. 4, memory units U3 and U4 are driven by a common data mask signal DQMB3, while the other memory units are individually driven by respective data mask signals. Parasitic capacitive load imbalance exists between the combined capacitance of memory units U3 and U4 and the individual capacitance of each of the other memory units.